In digital signal processing it is necessary to convert an analog signal into a digital format. To insure reasonable fidelity in this conversion, it is desirable to sample the analog signal at a rate substantially greater than analog signal bandwidth. These sampled signal values are then converted sample by sample at high speed into their equivalent digital values represented by "N" number of binary bits. Prior art ADCs, which typically use bipolar transistors, are able to operate at high rates (e.g., 50 MHz) and with 10-bit resolution. These ADCs require relatively large amounts of electrical power and are very costly. On the other hand, attempts to implement high speed, multi-bit ADCs with MOS technology have not been as successful as desired. Either cost was high because of poor chip yield or performance was substantially less than could be obtained using bipolar transistor technology.
A prior ADC, termed an "N-flash" ADC, simultaneously produces "N" data bits in parallel from a sampled analog voltage. The ADC comprises 2.sup.N -1 comparators which are closely matched to each other with each capable of high resolution. The ADC circuit momentarily connects all of these comparators at once to an input signal circuit. A decoder circuit coupled to all of the comparators then determines the values of the N bits corresponding to the analog value of the input signal being sampled at that instant. An advantage of this type of ADC is the high speed at which it can operate. An important disadvantage is relatively low impedance load (and corresponding large switching transients) caused by connecting all of the comparators to the input circuit at the same time. As an example, a 10 bit flash ADC uses 1023 comparators. Flash ADCs generate their reference analog voltages from a series-connected resistor circuit, commonly known as a resistor ladder. Typically, high resolution flash ADCs need to have the resistors in the ladder "trimmed" using, for example, a laser, to meet the tolerances required for high-resolution operation.
Another type of ADC is a successive approximation device. This type of ADC, in its simplest form, calculates an output digital value from a sampled analog potential one bit at a time, from the most significant bit to the least significant bit. As each bit of the output value is generated, the partial digital value is converted to an analog value by an internal digital to analog converter (DAC), and the analog value is subtracted from the original sample value. This difference value is then used to generate the next less significant bit of the digital output value. In this form, at least N comparison operations are needed to produce an N-bit digital value.
In a more complex form, this type of ADC employs N or more successive approximation stages in parallel, each operating on a respectively different staggered clocking phase. In this configuration, one N-bit digital output value is produced for each clock cycle. An exemplary successive approximation ADC is described in my earlier U.S. Pat. No. 5,272,481 entitled ANALOG TO DIGITAL CONVERTER which is hereby incorporated by reference for its teachings on successive approximation ADCs.
One problem with successive approximation ADCs is the accuracy of the analog value that is generated by the internal DACs. The reference voltages for these DACs are generated from a resistor ladder. Due to process variations, the values of these resistors may vary from specifications within an integrated circuit and from one integrated circuit to the next. Accordingly, the reference potentials used by the DACs may not be consistent within an ADC device or from one ADC to the next.